module top (
    input clk,
    input rst_n,
    output tx_data,
    output tx_valid
);

// Instance with tie-off ports
test_module u_test (
    .clk(clk),
    .rst_n(rst_n),
    .wire_port(),        // Unconnected port - should show as tie-off
    .normal_port(1'b0)   // Connected to constant - should show as tie-off
);

endmodule

module test_module (
    input clk,
    input rst_n,
    output wire_port,
    output normal_port
);

// Nothing here

endmodule